On Sat, 24 Jan 2004 17:38:45 +0000 (GMT)
Jim Lesurf wrote:

Probably not, in simple terms. However the problem is that the source clock
is 'buried' in the S/PDIF stream, so that stream is what you're given and
then you have to devise a suitable way to extract a suitable clock. Hence
you can apply careful design, but you have the problem to deal with if
receiving S/PDIF.

I would think that a good system would be something like this:

1) Extract the data (dont care how) whilst buffering the input samples used (inc. embedded clock).
2) Strip the data from the input samples now that we have decoded data and the original samples, leaving only the clock
3) use a PLL to lock onto this clock and provide a stable reference.

Surely this woiuld give you a clock signal with only an absolutely minimal amount of jitter (potentially less than the source clock).

Im not arguing it would be better than a single reference clock fed to all components, but it should eb pretty damn good...

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