Thanks, Serge. Looks like Crystal style the CS4398 as their 'flagship'
DAC (though I know at least one designer who prefers the CS4397). there
does seem to be an evaluation board. These references may help:

http://sharewave.com/en/products/pro/techs/T2.html details of Crystal
DAC chips
http://sharewave.com/en/pubs/rdDatasheet/CDB4398.pdf Evaluation board

There'a also a company that does a digital board with the CS4398 for
$495, but this does need in input chip.
http://www.aplhifi.com/index.html
". If you'd like to use I2S connection, you can send it directly to
the DAC board without digital receiver. The DAC accepts I2S, MSB and
LSB digital formats. It needs 8-9 volts filtered unregulated DC and it
has differential outputs from each DAC so you will need some sort of
filtering and tube or solid state stage with differential inputs. The
output amplitude on each output is around 1V RMS with 0db PCM"

On 2006-07-08, Andy Evans wrote:
Thanks, Serge. Looks like Crystal style the CS4398 as their 'flagship'
DAC (though I know at least one designer who prefers the CS4397). there
does seem to be an evaluation board. These references may help:

I believe I have a CS4396 in my Quad 99 CD-P and to my ears it comes
out fine. It's a 1999 design and the 2003 CS4398 has a few dB better
THD+N (and DSD input and an integrated volume control IIRC) but I suspect
we have reached the point where DAC performance can (if carefully
chosen and designed) be considered technically perfect for CD audio.
Performance may well now be dominated by what's used around the DAC chip
and how well it is laid out on the PCB.

However I would not normally use a non-upsampling DAC today (as per the
original list). Upsampling makes the reconstruction filter far simpler
and it is easier to avoid excessive phase angles in the audio band.
I am not sure about the audibility of phase lag at high audio frequencies
but I would try and avoid it on principle.

Also I would consider using an asynchronous upsampler chip in front of
the DAC chip in a stand-alone DAC. This would allow me (in theory -
I have not actually done a design) to keep a clean master clock close
to the DAC, rather than design a multi-stage PLL to derive a low jitter
DAC chip clock from a jittery SPDIF input.

--
John Phillips